(a) Field of the Invention
The present invention relates to a plasma etching apparatus and a plasma etching process mainly used for patterning an electrode material film of a ferroelectric capacitor. In particular, the invention relates to a plasma etching apparatus for fine patterning of the electrode material film while suppressing particle generation and a plasma etching process using the same.
(b) Description of Related Art
With the increase in density, functionality and speed of semiconductor integrated circuit devices in recent years, techniques of using a nonvolatile memory (e.g., FeRAM (Ferroelectric Random Access Memory)) have been proposed. In the nonvolatile memory, a ferroelectric film such as of SBT (strontium bismuth tantalate) or PZT (lead zirconic titanate) is used for a capacitor insulating film. Further, a simple substance film such as of platinum (Pt) or iridium (Ir) is used as a capacitor electrode material and a plasma dry etching technique mainly with a chlorine gas is employed for fine patterning thereof. However, it is extremely difficult to dry etch these electrode material films. The reason therefor is explained below.
Table 1 shows etching reaction products generated through a reaction between various kinds of electrode material films and a chlorine-containing etching gas, together with their boiling points.
TABLE 1SubstanceBoiling pointPtCl2581° C.PtCl4370° C.IrCl3763° C.SiCl4 58° C.
As shown in Table 1, if the electrode material film is a polysilicon film which is used for a general integrated circuit, SiCl4 is generated as an etching reaction product. Since SiCl4 has a boiling point as low as about 58° C., the product is easily gasified in an etching reaction chamber and emitted outside.
On the other hand, PtCl2, PtCl4 and IrCl3, which are products generated by a reaction between Pt or Ir and the chlorine-containing etching gas, have remarkably high boiling points as compared with SiCl4, and therefore these products are hard to gasify (vaporize). Accordingly, these reaction products do not go out of the chamber during the etching and remain adhered to the chamber wall. This will be a cause of particle generation in the later step. Especially in a plasma etching apparatus, a top plate of the chamber is generally opposed to a semiconductor wafer to be etched. Therefore, the reaction product adhered to the top plate may drop in the form of particles onto the wafer during the etching process to cause a defect in the fine pattern. This is a serious problem in manufacturing the semiconductor integrated circuits.
Among commonly used inductively coupled dry etching apparatuses, there is an apparatus comprising a Faraday shield electrode (hereinafter referred to as an FS electrode) arranged between the outer wall of the chamber and an inductively coupled coil (hereinafter referred to as an ICP coil) arranged to surround the outer wall to generate plasma of an etching gas in the chamber. In this apparatus, a voltage or high frequency power is applied to the FS electrode to prevent an insulating material forming the inner wall of the chamber from being etched by the plasma (for example, see Japanese Unexamined Patent Publication No. HEI 10-275694).
FIG. 5A shows a schematic configuration of an inductively coupled plasma treatment apparatus (etching apparatus) provided with a conventional FS electrode. As shown in FIG. 5A, an electrode 2 serving also as a wafer support is arranged inside a chamber 1 for performing plasma treatment such as dry etching. The electrode 2 is installed on the bottom of the chamber 1 via a support member 2a and a wafer 3 to be plasma-treated is placed on the electrode 2. Further, a high frequency bias voltage is applied to the electrode 2 from a high frequency power source 4.
At the top of the chamber 1, a top plate 7 made of quartz or ceramic is arranged to be opposed to the electrode 2 or the wafer 3. An inductively coupled coil 5 (hereinafter referred to as an ICP coil 5) for generating plasma in the chamber 1 is provided in proximity to the top surface of the top plate 7, i.e., the outer wall of the chamber 1. A high frequency voltage is supplied to the ICP coil 5 from a high frequency power source 6. Further, an FS electrode 40 having the aforesaid function is inserted between the ICP coil 5 and the top plate 7.
During the etching of the wafer 3, a suitably adjusted high frequency voltage is applied to the FS electrode 40 from a high frequency power source 10, which prevents the insulating material, especially forming the top plate 7, from being etched by plasma ion impact.
FIG. 5B is a plan view of the FS electrode 40 of the etching apparatus shown in FIG. 5A. In general, the FS electrode 40 is circular when viewed in plan as shown in FIG. 5B and is plate-shaped when viewed in section as shown in FIG. 5A.
The etching apparatus of FIG. 5A has an exhaust port 13 at the bottom thereof. Releasing a gate valve 12 brings a pressure-reduced state (a state where the pressure is lower than normal (atmospheric) pressure) in the chamber 1.
In contrast to the apparatus of FIG. 5A, in an apparatus not having the FS electrode, i.e., the Faraday shield, the generated plasma and the inductively coupled coil are coupled not only inductively but also capacitively. Accordingly, the insulating material such as quartz serving as the chamber wall is etched by the plasma. Especially in the vicinity of the inner wall of the chamber immediately below the ICP coil, electrons and ions in the plasma are accelerated in the direction vertical to the chamber inner wall by the high voltage applied to the coil at high frequency. Since the mass of the electrons is far smaller than that of the ions, the chamber inner wall is collided with the electrons more predominantly than the ions and thereby to be negatively charged. As a result, the ions carrying the opposite charge are attracted to the negatively charged area and the chamber wall material is etched by the ion impact.
On the other hand, in the etching apparatus configured as shown in FIG. 5A, the FS electrode 40 is provided between the ICP coil 5 and the insulating material for the inner wall of the chamber 1 and a voltage is applied to the FS electrode 40, thereby preventing the chamber wall from being etched. The FS electrode 40 is provided essentially for preventing the chamber inner wall from being wasted by the etching. If the voltage applied to the FS electrode 40 is optimized, an optimum capacitive coupling component is surely obtained at the area in the chamber 1 made of the insulating material and immediately below the ICP coil 5. In this case, a reaction product generated during the etching and adhered to the chamber inner wall can be etched by making use of a self-bias voltage due to the capacitive coupling component. That is, in the above-mentioned ideal case, the etching apparatus of FIG. 5A allows etching, while preventing the insulating material forming the chamber inner wall from being etched and controlling the adhesion of the reaction product generated during the plasma etching to some extent (i.e., reducing the generation of particles).